An integrated circuit (IC) typically comprises numerous semiconductor devices formed in single crystal silicon substrate. The semiconductor devices can be transistors, diodes, etc. The semiconductor devices must be connected with each other using conductive lines for the IC to function properly. The conductive lines are effectively wires that allow electrical communication between the semiconductor devices. Newer ICs, and especially microprocessors, are becoming increasingly complex. Because of the increasing number of semiconductor devices found in newer ICs, the number of conductive lines needed to connect the devices is also increasing. For complex ICs, a single layer of conductive lines is typically insufficient. As a result, the conductive lines must be layered upon one another to create layers of metallization. In order to isolate the conductive lines, an interlayer dielectric (ILD) is used. An ILD is an insulating layer such as silicon dioxide (SiO2), which prevents shorts and unwanted communication between the conductive lines.
One way to fabricate layers of metallization for an IC involves using what is known as a damascene process. The first procedure of a damascene process is to deposit an ILD. An ILD is deposited either directly on a substrate, or over another existing layer of metallization. Once the ILD is deposited, portions of the ILD may be etched away to form recessed features, such as trenches and vias, which will accommodate the conductive lines. A trench can be created to accommodate an interconnect, which can connect different regions of the IC. A via can be created to accommodate either a via or a contact, which will allow for communication between the interconnects of other layers or directly with the semiconductor devices in the substrate. A damascene process that creates either only trenches or vias is known as a single damascene process. A damascene process that creates both trenches and vias at once is known as a dual damascene process.
After the recessed features are created, metal, such as copper or aluminum, is deposited in them to create the conductive lines. In a damascene process, metal may be deposited using several well-known deposition techniques, including electroplating and electroless (EL) deposition. An electroplating process typically requires a conductive seed layer, such as a copper seed layer, to first be deposited over the recessed features. The substrate can then be dipped in a chemical bath. The seed layer creates a conductive path, and when a current is applied to the seed layer relative to the chemical bath, ions will adhere to the seed layer, and the recessed features will be filled. An EL deposition process does not require a seed layer. Instead, the ILD or another layer can be activated using a noble metal compound, such as a palladium (Pd) compound. Once the ILD or other layer is activated, the substrate can be deposited in a bath, and ions will adhere to the activated areas.
The electroplating and EL deposition processes typically deposit excess metal, which overfills the trenches and covers the top surface of the ILD. The excess metal can be removed using a chemical mechanical polishing (CMP) process. The CMP process involves introducing a chemical slurry to the surface of the ILD while using a rotating polishing pad to remove excess metal and planarize the surface of the ILD.
Because feature sizes in ICs have recently become so small, the conductive lines formed in layers of metallization are now separated by increasingly smaller gaps. An ILD comprises a dielectric material, which has a tendency to store charge, and can cause problems such as cross-talk and capacitive coupling between the conductive lines. A typical material used for an ILD is SiO2. SiO2 has a dielectric constant (k) of approximately 4.0. Due to the reduction in feature size and distance between the conductive lines, it has become desirable to use low-k dielectrics to reduce cross-talk and capacitive coupling. A low-k dielectric is typically defined as one having a dielectric constant of less than that of SiO2, or of less than 4.0. Air is the ultimate low-k dielectric, having a dielectric constant of approximately 1.0. Metallization layers having air gaps formed in them have been created to lower the dielectric constant of the layer. However, these layers typically are very weak, and can suffer from defects due to processing and other handling.
Diffusion and electromigration of metals such as copper and aluminum can cause the failure of interconnect structures. Further, interconnects can physically extrude into adjacent areas. These problems can become especially acute when using air gap structures because of their already structurally weak natures.